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J-K Flip-Flop

The J-K flip-flop is one of several typical triggers which controls its state transformation rules by means of signals from J and K. In a word, It accepts information before the cp falling edge, triggers a rollover on the falling edge, and the trigger is blocked after the falling edge.

Introduction to the Master-slave J-K flip-flop

1. Circuit structure

The Master-slave J-K  flip-flop is constructed on the Master-slave RS flip-flop, as shown below. At the R and S ports of the Master-slave RS flip-flop, a two-input AND gate G11 and G10 are added respectively. The Q port and input port through the AND gate output to the original S port, the input terminal is called J terminal. The Q port and the input terminal output through the AND gate to the original R port and the input port is called the K end.

2. The working principle

The above circuit can get S= JQ, R=KQ. PUT these condition into the characteristic equation of the RS trigger could get:

J= 1, K= 0, Qn+1= 1;

J= 0, K= 1, Qn+1= 0;

J=K=0, Qn+1=Qn;

J=K= 1, Qn+1= -Qn (Qn non);

From the above analysis, there is no constraint on Master-slave JK flip-flop. When J=K= 1, every time a clock pulse puts in, the trigger flips. The working state of the trigger is called the counting state, and the number of flipping times of the trigger can be used to calculate the number of input clock pulses.

The characteristics of the J-K flip-flop

  • Edge JK flip-flop has position, reset, retention (memory) and counting functions;
  • The edge JK trigger belongs to the pulse trigger mode, and the trigger flip occurs only at the negative jump of the clock pulse.
  • Since the receiving input signal is completed before the cp falling edge, triggering a rollover on the falling edge, and the trigger is blocked after the falling edge,so there is no change by one process and leads to good anti-interference performance and fast working speed.
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